Monday, 15 February 2010

ia 32 - IA-32 x86 data alignment -


Everything that I can find just told me that I should align because it can be more efficient, but I know The reason why I should do this because of the HAD issue IA-32 is that the address needs to be divisible by just 4, for example? Or because RAM can not only perform harmless data loss? Or?

There is no need for data alignment at IIA 32. A program will work properly with a four-byte integer, no matter where they are located. For example, a four byte integer may be located at the 1,2,3,4 address However, the machine executes more efficiently, for example, four byte integers are at four byte boundaries, so four byte integers A better option for starting an address is an address which is a multiple of 4.

This is a hardware related problem, usually the RAM module is thus Are linked to:

enter image details here

If coalition is used, then module 1, 2, 3 and 4 are selected at the same time and thus 32 bits can be read in a memory read cycle.

If there is an uncontrolled reach, then let's say 2 bytes for example, then module 1, 2, 3 and 4 are selected in the first reading cycle, where only 2 bytes (less We are reading 2 bytes of data) (Module 3 and 4); The next reading cycle module has been selected on 5, 6, 7 and 8, where only less than 2 bytes (the maximum of 2 bytes of data we are getting) are read.

A more detailed view of the RAM module (Simplified for 4-bit machines with capacity for 4 words).

4-bit RAM

In this diagram, this very clear That you can only select a line of flip-flops because the decoder will only activate one output line, and 3 will remain at 0.

Note that some architectures force you to align all memory access by throwing a bug error if reaching an unknown address (i.e., mieps), while many other necessary cycles need to have the necessary data (I.e. x86), although of course this extra hardware (usually) is required.


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