c - Rx side interface between PHY and MAC layer -

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I'm out of motivation, so looking for some advice I made TxRx at Zynq SOC (the whole PHY layer is on FPGA - PL run). My RX (I have already created the interface for TX) is providing me 8 bit data output and length of packet signal, now I am making the interface between FPGA and processor. I have two ideas, but I do not know if they are correct, in a way, after the RX, the buffer should be inserted on the FPGA portion unless I get all the Nx 8 bits which represent a full packet. Another way to create buffer on the ARM-PS part and write each 8 bits by DMA will be. Do you think there is a better way of doing things? There can be just 32 or 64 bits between PS and PLL.